With the introduction of CMOS circuits with geometries below 0.35 microns, lower power supply voltages have become necessary to maintain device reliability. Consequently, supply voltage have decreased from 5 volts to 3.3 volts or less. However, many interface (bus) signals still use zero to 5 volt logic levels. Logic processor input/output (I/O) circuits therefore are required to be "voltage friendly", i.e., they may provide (source) a zero to 3.3 volt signal but must accept a zero to 5 volt signal.
In lieu of being voltage friendly, the circuitry can be divided into "core" circuits and I/O circuits, where the "core" logic operates at the lower 3.3 volts, and the I/O circuits operate at 5 volts. To facilitate signal level compatibility, a voltage level shifter circuit similar to FIG. 1 (Prior Art) is used within the I/O circuits.
Furthermore, the introduction of very high speed, small geometry SIMOX CMOS circuits (where each transistor is electrically isolated by silicon dioxide) enables even lower voltages for the `core` circuits. Many of these circuits are required to operate from a single battery in such applications as pagers). Other applications use a single battery (0.8 to 1.5 volts) to power the core circuits and a double battery (1.5 to 3 volts) to power the I/O circuits. A flexible core to I/O voltage level shifter is required that can accept 0.8 volt logic signals as an input and translate to either 0.8 volts or 0.8 to 3 volts output signals. The large voltage spread may result from the core battery being low (end of life) and the I/O battery(ies) being new). As shall be described below, as the battery or batteries are drained, the prior art level shifter circuitry becomes relatively slow.
Specifically, FIG. 1 depicts a schematic diagram of a prior art level shifter 100 comprising a P-type crisscross pull-up circuit 102 and an N-type pull-down circuit 104. In response to an digital input signal V.sub.in the P-type circuit 102 pulls the output signal up to a predefined voltage (e.g., approximately VDDE) and, alternately, the N-type pull-down circuit 104 pulls the output voltage down to a predefined voltage (e.g., approximately zero).
More specifically, the input signal V.sub.in is coupled to two paths, where the first path carries the input signal to an inverter 106 and the second path carries the input signal directly to the gate electrode of transistor N.sub.2 of the N-type pull-down circuit 104. The inverted output of the inverter 106 is coupled to the gate electrode of transistor N.sub.1 of the N-type pull-down circuit 104. As such, each transistor of the N-type pull-down circuit 104 is driven with an input signal that is inverted with respect to the other input. To ensure timing synchronization a delay component may be used in the second path to transistor N.sub.2 such that the input signal at each transistor is synchronized and "clock skew" is avoided.
The source electrode of each N-type transistor is connected to ground and the drain electrodes are coupled to the P-type pull-up circuit 102, i.e., the N-type transistors are arranged in a common source configuration. The P-type circuit is a crisscross design containing a pair of P-type transistors P.sub.1 and P.sub.2. The gate electrode of transistor P.sub.1 is connected to the drain electrode of transistor P.sub.2. Similarly, the gate electrode of transistor P.sub.2 is connected to the drain electrode of transistor P.sub.1. The source electrodes of each P-type transistor are coupled to a DC voltage supply VDDE.
In operation, in response to each transition of the input signal V.sub.in, alternately, the P-type circuit 102 pulls the output signal up to approximately VDDE and the N-type circuit 104 pulls the output signal down to approximately ground. As such, the output signal switches between ground and VDDE with each cycle of the input signal.
In level shifters using such P-type crisscross circuits, the salient feature is the ability to consume minimal power during the transition times. For such level shifters to operate properly, the P-type transistors are "weak" compared to the N-type transistors, i.e., the p-type transistors have significantly lower drive current-capability so the N-type pull-down transistors can overcome the P-type pull-up function. Consequently, the output transitions suffer from relatively slow rise time as well as delay time for low-end voltage supply. This relative slowness is further exacerbated when the battery level at VDDE is low (e.g., decreases to 0.8 volts). In addition, the output signal also suffers from coupling effect gating through from the physically larger N-type pull-down transistors.
FIG. 2 depicts these detrimental characteristics of slow rise time and substantial delay in a plot of the output signal from the prior art level shifter of FIG. 1. The plot 200 depicts time (axis 202) versus output voltage magnitude (axis 204). The switching time delay is approximately 3 nanoseconds and the rise time can be as much as 6 nanoseconds. These data were taken using a 50 megahertz square wave input signal with VDDE fixed at 0.8 volts (simulating a battery with very low voltage) and a load capacitance of 0.1 picofarads. Such delay and rise time duration is well-known to result in excessive power consumption by the level shifter during the switching times.
Therefore, a need exists in the art for a crisscross level shifter having improved rise time, improved switching delay and low power consumption.